(1) Field of the Invention
The present invention relates to a high speed flip-flop circuit and, more particularly, to a flip-flop circuit having a CMOS inverter (hereinafter referred to as a "CMOS flip-flop circuit").
(2) Description of the Related Art
An example of a conventional high speed CMOS flip-flop circuit is shown in FIG. 1. The CMOS flip-flop circuit shown is a dynamic type flip-flop circuit. As shown in the drawings, complementary clock signals are inputted to clock signal input terminals 6 and 7, respectively, and when a CMOS transfer gate circuit 9 composed of a complementary pair of P-channel and N-channel transistors turns on in response to the clock signals, the data signal applied to a data input terminal 4 is latched and then inverted by an inverter 1 with the inverted signal being outputted at a data output terminal 5. Thereafter, when the transfer gate circuit 9 turns off, this state is held.
FIG. 2 shows a conventional example of a master-slave type flip-flop circuit wherein two stage flip-flop circuits each of which is the same as that shown in FIG. 1 are connected in series and wherein an output of the second stage flip-flop circuit (composed of a transfer gate circuit 19 and an inverter 11) is inverted by an inverter 21 and fed back to a transfer gate circuit 9, whereby a T-type flip-flop circuit is formed. In this T-type flip-flop circuit, when the complementary clock signals are applied to the clock signal input terminals 6 and 7, a signal whose frequency is half that of the complementary clock signal is outputted at the output terminal 5.
Another CMOS flip-flop circuit capable of operating at a high speed is shown in FIG. 3. The CMOS flip-flop circuit shown in FIG. 3 is disclosed in a publication "Multigigahertz CMOS Dual-Modulus Prescalar IC" (by H. Cong et al, in IEEE Sc. Vol. 23 No. 5, October 1988, pages 1189-1194).
In the above CMOS flip-flop circuit, the master-slave configuration is realized by use of two hysteresis inverters, one being composed of inverters 1, 2 as a first hysteresis inverter and the other being composed of inverters 11, 12 as a second hysteresis inverter. The clock input signal adopts a single-phase signal and not complementary signals. The clock signal inputted to the clock signal input terminal 6 is applied to the gates of P-channel transistors 31, 32 for the master stage and the same is applied to the gate of an N-channel transistor 35 for the slave stage. The signals inputted to the data input terminals 4, 8 are the complementary signals which are applied to the gates of N-channel transistors 33, 34 and which cause the P-channel transistors 31, 32 to function so that such complementary data signals can change the input and output potentials of the first hysteresis inverter (1, 2).
N-channel transistors 36, 37 function as a differential pair having a common source connection and control the data inputs of the slave flip-flop stage. The transistor 35 functions so that the data inputs can change the input and output potentials of the second hysteresis inverter (11, 12).
In the conventional dynamic type flip-flop circuits shown in FIGS. 1 and 2, there is no particular holding circuit for data signals, and the data is held and stored in the form of a charge to a gate capacitance of the field effect transistors constituting the inverter 1. Therefore, although the circuit can operate at a comparatively high speed, a low speed operation conversely results in loss of the charge thereby causing malfunctions to occur. Also, since the flip-flop circuits shown in FIGS. 1 and 2 are CMOS circuits, the above mentioned gate capacitance must be charged and discharged with the signals fully swinging to the power supply voltage and this has limited the realization of a circuit capable of operating at a high speed.
The master-slave flip-flop circuit shown in FIG. 3 involves the problem that the level of the single-phase clock signal to be applied to the clock signal input terminal 6 cannot be decided by a single standard since the P-channel transistors 31, 32 are used for the master flip-flop stage, and another type, that is, the N-channel transistor 35 is used for the slave flip-flop stage. This problem arises because threshold values of the P-channel transistors are established in the course of manufacture of the component transistors with no correlation being made with the threshold value of the N-channel transistor and also because such threshold values can vary in the course of manufacture. The variation thus occurring has influence on the production yield at the fabrication or integration of the device. Further, since the transistor 35 is connected in series with the differential pair transistors 36, 37, this results in a disadvantage of the realization for a low power supply voltage operation. A further disadvantage is that the number of elements required for the flip-flop circuit is large.